// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//======================================================================

// Include common routines
#include <verilated.h>

// Include model header, generated from Verilating "top.v"
#include "verilator_test.h"

int main(int argc, char** argv, char** env) {
  // See a similar example walkthrough in the verilator manpage.

  // This is intended to be a minimal example.  Before copying this to start a
  // real project, it is better to start with a more complete example,
  // e.g. examples/c_tracing.

  // Prevent unused variable warnings
  if (false && argc && argv && env) {}

  // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
  verilator_test* top = new verilator_test;

  // Simulate until $finish
  while (!Verilated::gotFinish()) {

    // Evaluate model
    top->eval();
  }

  // Final model cleanup
  top->final();

  // Destroy model
  delete top;

  // Return good completion status
  return 0;
}
